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april 2007 rev 5 1/22 1 M41T0 serial real time clock features counters for seconds, minutes, hours, day, date, month, years, and century 32khz crystal oscillator integrating load capacitance (12.5pf) providing exceptional oscillator stability and high crystal series resistance operation oscillator stop detection monitors clock operation serial interface supports i 2 c bus (400khz protocol) low standby current 0.9a (typ@3v) 2.0 to 5.5v clock operating voltage special software programmable output software clock calibration to compensate crystal deviation due to temperature operating temperature of ?40 to 85c 8 1 so8 (m) www.st.com
contents M41T0 2/22 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 bus not busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 start data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.3 stop data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.4 data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.5 acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
M41T0 list of tables 3/22 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. so8 ? 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . 19 table 10. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
list of figures M41T0 4/22 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. alternate read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 figure 10. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. ac testing input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. so8 ? 8 lead plastic small outline, 150 mils body width, package mechanical drawing. . . 19
M41T0 summary description 5/22 1 summary description the M41T0 real time clock is a low power serial real time clock with a built-in 32.768khz oscillator (external crystal controlled). eight registers are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. addresses and data are transferred serially via a two-line bi-directional bus. the built-in address register is incremented automatically after each write or read data byte. the M41T0 is supplied in 8 lead plastic small outline package. figure 1. logic diagram figure 2. soic connections 1. nf pin must be tied to v ss . table 1. signal names osci oscillator input ocso oscillator output out output driver (open drain) sda serial data address input / output scl serial clock nf (1) 1. nf pin must be tied to v ss . no function v cc supply voltage v ss ground ai07028 osci v cc M41T0 v ss scl osco sda out 1 sda v ss scl out osco osci v cc nf (1) ai07029 M41T0 2 3 4 8 7 6 5
summary description M41T0 6/22 figure 3. block diagram ai07030 seconds oscillator 32.768 khz serial bus interface divider control logic address register minutes century/hours day date month year control osci osco out v cc v ss scl sda 1 hz
M41T0 operation 7/22 2 operation the M41T0 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 8 bytes contained in the device can then be accessed sequentially in the following order: 1. seconds register 2. minutes register 3. century/hours register 4. day register 5. date register 6. month register 7. years register 8. control register 2.1 2-wire bus characteristics this bus is intended for communication between different ics. it consists of two lines: one bi-directional for data signals (sda) and one for clock signals (scl). both the sda and the scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be inte rpreted as control signals. accordingly, the following bus conditions have been defined: 2.1.1 bus not busy. both data and clock lines remain high. 2.1.2 start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition. 2.1.3 stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition.
operation M41T0 8/22 2.1.4 data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition, a device that gives out a message is called ?transmitter?, the receiving device that gets the message is called ?receiver?. th e device that controls the message is called ?master?. the devices that are controlled by the master are called ?slaves?. 2.1.5 acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case, the transmitter must leave the data line high to enable the master to generate the stop condition. figure 4. serial bus data transfer sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition
M41T0 operation 9/22 figure 5. acknowledgement sequence figure 6. bus timing requirements sequence 1. p = stop and s = start ai00601 data output by receiver data output by transmitter sclk from master start clock pulse for acknowledgement 12 89 msb lsb ai00589 sda p tsu:s t tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
operation M41T0 10/22 2.2 read mode in this mode, the master reads the M41T0 slave after setting the slave address (see figure 7 ). following the write mode control bit (r/w = 0) and the acknowledge bit, the word address an is written to the on-chip address pointer. next the start condition and slave address are repeated, followed by the read mode control bit (r/w = 1). at this point, the master transmitter becomes the master receiver. the data byte which was addressed will be transmitted and the mast er receiver will send an ac knowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge bit. the M41T0 slave transmitter will now pl ace the data byte at address a n+1 on the bus. the master receiver reads and acknowledges the new byte and the address pointer is incremented to a n+2 . this cycle of reading consecutive addresses will continue until the mast er receiver sends a stop condition to the slave transmitter. an alternate read mode may also be implemented, whereby the master reads the M41T0 slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 9 on page 12 ). table 2. ac characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). min typ max unit f scl scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 600 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:dat data setup time 100 ns t hd:dat (2) 2. transmitter must internally provi de a hold time to bridge the undefined region (300ns max.) of the falling edge of scl. data hold time 0 s t su:sto stop condition setup time 600 ns t buf time the bus must be free before a new transmission can start 1.3 s
M41T0 operation 11/22 2.3 write mode in this mode the master transmitter transmits to the M41T0 slave receiver. bus protocol is shown in figure 10 on page 12 . following the start condition and slave address, a logic '0' (r/w = 0) is placed on the bus and indicates to the addr essed device that word address an will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the M41T0 slave receiver will se nd an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see figure 7 ). figure 7. slave address location figure 8. read mode sequence ai00602 r/w slave address start a 01000 11 msb lsb ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack
operation M41T0 12/22 figure 9. alternate read mode sequence figure 10. write mode sequence ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
M41T0 clock operation 13/22 3 clock operation the M41T0 is driven by a quartz controlled oscillator wi th a nominal frequency of 32.768khz. the accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the rtc. the M41T0 is tested to meet 35 ppm with nominal crystal. the eight-byte clock register (see table 3 on page 14 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. seconds, minutes, and hours are contained within the first three registers. bits d6 and d7 of clock register 2 (hours register) contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0', cb will not toggle. bits d0 through d2 of register 3 contain the day (day of week). registers 4, 5 and 6 contain the date (day of month), month and years. the final register is the control register. bit d7 of register 0 contains the st op bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expected to spend a significant amount of time on the shelf, the oscillator may be stop ped to reduce current drain. when reset to a '0' the oscillator restarts within four seconds (typically one second). the seven clock registers may be read one byte at a time, or in a sequential block. the control register (address location 7) may be accessed independently. provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. if a clock addr ess is being read, an update of the clock registers will be delayed by 250ms to allow the read to be completed before the u pdate occurs. this will prevent a transition of data during the read. note: this 250ms delay affects only the clock register update and does not alter the actual clock time. 3.1 output driver pin the out pin is an output driver that reflects the contents of d7 of the control register. in other words, when d7 of location 7 is a '0' then the out pin will be driven low. note: the out pin is open drain which requires an external pull-up resistor. 3.2 oscillator stop detection if the oscillator fail (of) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. th is bit will be set to '1' any time the oscillator stops. the following conditions can cause the of bit to be set: the first time power is applied (defaults to a '1' on power-up). the voltage present on v cc is insufficient to support oscillation. the st bit is set to '1.' external interference or removal of the crystal. this bit will remain set to '1 ' until written to logic '0.' the oscillator must start and have run for at least 4 seconds before a ttempting to reset the of bit to '0.' this function operates both under normal power and in battery back-up.
clock operation M41T0 14/22 3.3 initial power-on defaults upon initial application of powe r to the device, the out bit and of bit will be set to a '1,' while the st bit will be set to '0.' all other re gister bits will initially power-on in a random state. table 3. register map (1) 1. keys: st = stop bit out = output level x = don?t care 0 = must be set to '0.' ceb = century enable bit cb = century bit of = oscillator fail bit address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 0 st 10 seconds seconds seconds 00-59 1 of 10 minutes minutes minutes 00-59 2ceb (2) 2. when ceb is set to '1', cb toggles from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set).when ceb is set to '0', cb does not toggle. cb 10 hours hours century/hours 0-1/00-23 3 x x x x x day day 01-07 4 x x 10 date date date 01-31 5 x x x 10 m. month month 01-12 6 10 years years year 00-99 7 out 0 x x x x x x control
M41T0 maximum rating 15/22 4 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 4. absolute maximum ratings symbol parameter value unit t stg storage temperature (v cc off, oscillator off) ?55 to 125 c v cc supply voltage ?0.3 to 7 v tsld (1) 1. reflow at peak temperature of 255c to 260c for < 30 seconds (total thermal budget not to exceed 180c for between 90 and 150 seconds). lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to v cc + 0.3 v i o output current 20 ma p d power dissipation 1 w
dc and ac parameters M41T0 16/22 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. figure 11. ac testing input/output waveform table 5. operating and ac measurement conditions (1) 1. output hi-z is defined as the point where data is no longer driven. parameter M41T0 unit supply voltage (v cc ) 2.0 to 5.5 v ambient operating temperature (t a ) ?40 to 85 c load capacitance (c l ) 100 pf input rise and fall times 5ns input pulse voltages 0.2v cc to 0.8v cc v input and output timing ref. voltages 0.3v cc to 0.7v cc v table 6. capacitance symbol parameter (1)(2) 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested 2. at 25c, f = 1mhz. min max unit c in input capacitance (scl) 7 pf c out (3) 3. outputs deselected. output capacitance (sda, out) 10 pf t lp low-pass filter input ti me constant (sda and scl) 50 ns ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc
M41T0 dc and ac parameters 17/22 table 7. dc characteristics sym parameter test condition (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.0 to 5.5v (except where noted). min typ max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current frequency (scl) = 400khz 3.0v 35 55 a 5.5v 130 200 a i cc2 (2) 2. at 25c. supply current (standby) all inputs = v cc ? 0.2v frequency (scl) = 0hz 3.0v 0.9 1.2 a 5.5v 31 a v il input low voltage ?0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc + 0.3 v v ol output low voltage i ol = 3ma 0.4 v output low voltage (open drain) i ol = 10ma 0.4 v table 8. crystal electrical characteristics symbol parameter (1)(2) 1. these values are externally s upplied. stmicroelectroni cs recommends the kds dt-38: 1ta/1tc252e127, tuning fork type (thru-hole) or the dmx-26s: 1tjs 125fh2a212, (smd) quartz crystal for industrial temperature operations. kds can be contacted at k ouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. load capacitors are integrated within the M41T0. circ uit board layout considerations for the 32.768khz crystal of minimum trace lengths and isolation from rf generating signal s should be taken into account. min typ max unit f o resonant frequency 32.768 khz r s series resistance 60 (3) 3. r s = 40k when v cc 2.5v. k c l load capacitance 12.5 pf
package mechanical information M41T0 18/22 6 package mechanical information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
M41T0 package mechanical information 19/22 figure 12. so8 ? 8 lead plastic small outline, 150 mils body width, package mechanical drawing 1. drawing is not to scale. table 9. so8 ? 8 lead plastic small outline, 150 mils body width, package mechanical data 1. drawing is not to scale. symbol millimetres inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k 08 08 l 0.40 1.27 0.016 0.050 l1 1.04 0.041 so-a e 8 ddd b e a d c l a1 1 h h x 45? a2
part numbering M41T0 20/22 7 part numbering for a list of additional options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 10. ordering information scheme example: m41t 0 m 6 f device type m41t supply voltage and write protect voltage 0: v cc = 2.0 to 5.5v package m = so8 (150mils width) temperature range 6 = ?40 to 85c shipping method e = lead-free package (ecopack ? ), tubes f = lead-free package (ecopack ? ), tape & reel
M41T0 revision history 21/22 8 revision history table 11. document revision history date rev. # revision details february 2003 1.0 first issue 18-feb-03 1.1 add pb-free information ( ta bl e 4 , ta bl e 1 0 ); update package information ( feature summary on page 1 , figure 13 ; ta bl e 1 0 ) 01-apr-03 1.2 fix package outline and data ( feature summary on page 1 , figure 13 , ta b l e 1 0 , ta b l e 1 0 ) 10-apr-03 1.3 revert to previous package ( feature summary on page 1 , figure 13 , ta b l e 1 0 , ta b l e 1 0 ) 30-oct-03 1.4 remove footnote ( ta b l e 4 ) 30-jun-2004 2.0 shipping method options updated and note 1 removed from ta bl e 1 0 : ordering information scheme . datasheet put in new template. 23-jul-2004 3.0 content correct ed from m41t80 to M41T0. 22-aug-2006 4 changed document to new template; amalgamated diagrams in feature summary on page 1 ; updated package mechanical data in section 6: package mechanical information ; ta b l e 1 0 ecopack compliant; small text changes for entire document 04-apr-2007 5 updated packaging information that only so8 package available (cover page and table 10: ordering information scheme ).
M41T0 22/22 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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